• DocumentCode
    894908
  • Title

    Simulation-Based Bug Trace Minimization With BMC-Based Refinement

  • Author

    Chang, Kai-Hui ; Bertacco, Valeria ; Markov, Igor L.

  • Author_Institution
    Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI
  • Volume
    26
  • Issue
    1
  • fYear
    2007
  • Firstpage
    152
  • Lastpage
    165
  • Abstract
    Finding the cause of a bug can be one of the most time-consuming activities in design verification. This is particularly true in the case of bugs discovered in the context of a random-simulation-based methodology, where bug traces, or counterexamples, may be several hundred thousand cycles long. In this paper, BUg TRAce MINimization (Butramin), which is a bug trace minimizer, is proposed. Butramin considers a bug trace produced by a random simulator or semiformal verification software and produces an equivalent trace of shorter length. Butramin applies a range of minimization techniques, deploying both simulation-based and formal methods, with the objective of producing highly reduced traces that still expose the original bug. Butramin was evaluated on a range of designs, including the publicly available picoJava microprocessor, and bug traces up to one million cycles long. Experiments show that in most cases, Butramin is able to reduce traces to a very small fraction of their initial sizes, in terms of cycle length and signals involved. The minimized traces can greatly facilitate bug analysis and reduce regression runtime
  • Keywords
    integrated circuit testing; microprocessor chips; regression analysis; Butramin; bug trace minimization; counterexample minimization; error diagnosis; picojava microprocessor; random simulation; regression runtime; semiformal verification software; Analytical models; Computational modeling; Computer bugs; Context modeling; Electronic design automation and methodology; Integrated circuit synthesis; Microprocessors; Minimization methods; Runtime; Testing; Bug trace minimization (Butramin); counterexample minimization; error diagnosis; verification;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.882511
  • Filename
    4039508