DocumentCode
894928
Title
A case for direct-mapped caches
Author
Hill, Mark D.
Author_Institution
Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
Volume
21
Issue
12
fYear
1988
Firstpage
25
Lastpage
40
Abstract
Direct-mapped caches are defined, and it is shown that trends toward larger cache sizes and faster hit times favor their use. The arguments are restricted initially to single-level caches in uniprocessors. They are then extended to two-level cache hierarchies. How and when these arguments for caches in uniprocessors apply to caches in multiprocessors are also discussed.<>
Keywords
buffer storage; multiprocessing systems; performance evaluation; storage allocation; storage management; buffer storage; cache sizes; direct-mapped caches; hit times; multiprocessors; performance evaluation; single-level caches; storage allocation; storage management; two-level cache hierarchies; Capacitive sensors; Central Processing Unit; Computer aided instruction; Computer aided software engineering; Costs; Hardware; Read-write memory; Reduced instruction set computing; Sun;
fLanguage
English
Journal_Title
Computer
Publisher
ieee
ISSN
0018-9162
Type
jour
DOI
10.1109/2.16187
Filename
16187
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