Bounding signal probabilities for testability measurement using conditional syndromes

Author

Kapur, Rohit ; Mercer, M. Ray

Author_Institution

IBM, Endicott, NY, USA

Volume

41

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1580

Lastpage

1588

Abstract

An algorithm for bounding the random pattern testability of individual faults in a circuit is proposed. Auxiliary gates for bounding the testability are constructed, converting the problem into one of determining the signal probability at the output of the auxiliary gate. The results presented are in terms of lower bounds of the testabilities of faults. The bounds generated by the algorithm can be used by designers to identify pseudorandom pattern resistant faults, to enable them to modify the circuit structure to make the faults easy to detect, and, hence, to increase the fault coverage

Keywords

built-in self test; circuit analysis computing; computational complexity; integrated circuit testing; auxiliary gate; bounding algorithm; circuit faults; circuit structure; conditional syndromes; lower bounds; pseudorandom pattern resistant faults; random pattern testability; signal probabilities; testability measurement; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Helium; Terrorism;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.214666

Filename

214666