An experimental 1 Mbit DRAM based on high S/N design

The key to achieving 1-Mb is higher signal-to-noise ratio, while maintaining single 5-V operation even for small feature-size MOSTs. To meet this requirement, three developments are proposed: a corrugated capacitor (memory) cell, a multidivided data line structure, and an on-chip voltage limiter. The results include an improvement in signal-to-noise ratio by a factor of about 22 and provision for single 5-V operation. These techniques have been proven to be useful through the design and evaluation of an experimental 21-/spl mu/m/SUP 2/-cell, single-5-V, 1-Mb NMOS DRAM. Its significant features include: an access time of 90 ns, a power dissipation of 295 mW at 260 ns cycle time, and a 46 mm/SUP 2/ chip area.