Title :
A subnanosecond 8K-gate CMOS/SOS gate array
Author :
Tanaka, Shigeru ; Iwamura, Jun ; Ohno, Junichi ; Maeguchi, Kenji ; Tango, Hiroyuki ; Doi, Katsuyuki
Abstract :
An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.
Keywords :
CMOS integrated circuits; Cellular arrays; Integrated logic circuits; cellular arrays; integrated logic circuits; CMOS logic circuits; CMOS process; CMOS technology; Control systems; Delay; Inverters; Large scale integration; Logic devices; Parasitic capacitance; Semiconductor devices;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052205
