DocumentCode :
896921
Title :
A radix 4 delay commutator for fast Fourier transform processor implementation
Author :
Swartzlander, Earl E., Jr. ; Young, Wendell K W ; Joseph, Saul J.
Volume :
19
Issue :
5
fYear :
1984
Firstpage :
702
Lastpage :
709
Abstract :
The development is described of a semicustom delay commutator circuit to support the implementation of high-speed fast Fourier transform processors based on the radix 4 pipeline FFT algorithm of J.H. McClellan and R.J. Purdy (1978). The delay commutator is a 108000-transistor circuit comprising 12288 shift register stages and approximately 2000 gates of random logic realized with 2.5-micrometer design rule CMOS standard cell technology. It operates at a 10-MHz clock rate, which processes data at a 40-MHz rate. The delay commutator is suitable for implementing processors that compute transforms of 16, 64, 256, 1024, and 4096 (complex) points. It is implemented as a 4-bit-wide data slice to facilitate cocatenation to accommodate common data word sizes and to use a standard 48-pin dual-in-line package.
Keywords :
CMOS integrated circuits; Computerised signal processing; Delay circuits; Digital integrated circuits; Fast Fourier transforms; computerised signal processing; delay circuits; digital integrated circuits; fast Fourier transforms; CMOS logic circuits; CMOS technology; Clocks; Delay; Fast Fourier transforms; Logic design; Logic gates; Packaging; Pipelines; Shift registers;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1984.1052211
Filename :
1052211
Link To Document :
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