An algorithm for CMOS timing and area optimization

Delay-time optimization for integrated circuits is discussed. A design truly optimized for delay time is seldom practical because the silicon area increases very rapidly when the minimum delay time is approached. The author presents an algorithm which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain. A computer software based on this algorithm can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors. Some basic assumptions are made in this algorithm in order to keep the mathematics manageable. Consequently, some random parameters related to layout and interconnection are not addressed. The intended use of this algorithm is to guide the designer to arrive at an approximately optimized design during the logic definition stage and before the layout stage. Later, when the layout is completed, a circuit simulator should be used to fine-tune the design by incorporating these random layout parameters.