DocumentCode
897159
Title
An 8 bit, 100 ms/s flash ADC
Author
Yoshii, Yoji ; Asano, Katsuaki ; Nakamura, Minoru ; Yamada, Chikara
Volume
19
Issue
6
fYear
1984
Firstpage
842
Lastpage
846
Abstract
An 8-bit flash ADC capable of operation at a sampling rate higher than 100 MHz with only 1.2 W of power dissipation is described. This good performance is realized using: (1) a small transistor utilizing oxide isolation and a thick field oxide process with small parasitic capacitances; (2) an optimized design for speed, accuracy, and power; and (3) a simple comparator design with small component count. Analog input capacitance of 35 pF and full-scale bandwidth of higher than 40 MHz were obtained. An error under the beat frequency test was eliminated by decoupling the master and the slave latches of the comparator.
Keywords
Analogue-digital conversion; Comparators (circuits); analogue-digital conversion; comparators (circuits); Circuit simulation; Delay effects; Fabrication; Latches; Parasitic capacitance; Power dissipation; Predictive models; Resistors; Sampling methods; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1984.1052235
Filename
1052235
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