A high speed dual port memory with simultaneous serial and random mode access for video applications

A 64K/spl times/1 NMOS dynamic RAM which is interfaced in an on-chip 256-bit high-speed shift register is described. The device allows parallel transfer of 256 bits from a selected row in memory to the shift register in a normal RAS cycle time. Subsequently, the device provides simultaneous and asynchronous access from both the DRAM and the serial ports. The shift register can operate at a typical frequency of 33 MHz. When used in conjunction with multiple devices of the same design, a high-resolution bit-mapped video display system can be achieved with video bandwidths beyond 100 MHz. The dual-ported nature of the device allows a graphics processor to operate on the DRAM portion of the device while the shift register simultaneously provides a video data stream to a video display system.