The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-μm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺ regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺ and p⁺ junction depths are 0.22 μ and of 8 Ωsq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.