Defect and fault tolerant interconnection strategies for WASP devices

Author

Hussaini, Mohammed B A ; Bolouri, Hamid ; Lea, R. Mike

Author_Institution

Brunel Univ., Uxbridge, UK

Volume

18

Issue

3

fYear

1995

fDate

8/1/1995 12:00:00 AM

Firstpage

416

Lastpage

423

Abstract

While WSI-based devices continue to be of particular interest for applications with severe performance, size, weight, power, cost, and reliability requirements, various implementation constraints in the past, including interconnect defect occurrences, have prevented their successful realization. This paper presents an investigation into defect and fault tolerant interconnect strategies for a representative WSI device, WASP (WSI Associative String Processor)

Keywords

associative processing; fault tolerant computing; integrated circuit interconnections; integrated circuit reliability; microprocessor chips; wafer-scale integration; WASP devices; WSI associative string processor; WSI-based devices; defect tolerant interconnection; fault tolerant interconnection strategies; reliability requirements; Application software; Fault tolerance; Integrated circuit interconnections; LAN interconnection; Multiprocessor interconnection networks; Power system interconnection; Power system reliability; Prototypes; Silicon; Wafer scale integration;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1070-9894

Type

jour

DOI

10.1109/96.404097

Filename

404097