Influence of process parameter variations on the signal distribution behavior of wafer scale integration devices

With decreasing geometries of MOS transistors in VLSI devices, the influence of fluctuations of process parameters during manufacturing will become more and more important, because process tolerances are not proportionally scaled to geometries. These fluctuations result in a performance spread of the devices produced by a certain process. For instance the clock rate of a microprocessor as a typical performance indicator, can vary in a wide range. One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. In the following paper, an efficient method for accurate prediction of the performance spread of integrated circuits is discussed and demonstrated by simulations. All the simulations are verified by measurements on a test-circuit with a huge number of test devices. The method is applied to different signal distribution networks of wafer scale integration devices to show the sensitivity of performance to these variations