Test vehicle for a wafer-scale field programmable gate array

A test vehicle for a wafer scale field programmable gate array (FPGA) has been designed which has the potential to significantly expand FPGA capabilities. A symmetrical RAM-programmable FPGA, look-up table-based logic block and segmented channel routing are used. In this paper, the practical problems inherent to wafer scale FPGA´s are investigated: i.e., redundancy, power shorts, clock distribution, cell and bus testing, and inter-cell delay. The laser-link process is used to interconnect working cells and form a defect-free array of FPGA cells. The defect avoidance algorithm is designed to minimize the delay between working cells, an important parameter for FPGA users