A methodology for the fast and testable implementation of state diagram specifications [logic design]

A methodology is presented for the hierarchical structured design of state diagram specifications. It is based on a set of restrictions on the composition of the hierarchy that allows a design to be proven correct by construction. Furthermore, silicon primitives are introduced that permit a direct mapping of asynchronous and synchronous state diagrams. Special attention is paid to the use of scanpath testability enhancement. The design methodology and implementation technique combined facilitate a fast and area efficient integration of control structures. From the development of a DRAM controller IC, it is shown how layout design can be automated through several phases of standard cell design, permitting silicon compilation in the near future.