Optimized ESD protection circuits for high-speed MOS/VLSI

New electrostatic discharge (ESD) protection circuits for MOPS/VLSI provide typical 2.7-ns delays and protection against voltage spikes up to 2200 V (limit of test circuit) in some cases. These circuits contain some traditional elements plus new features including a gate-drain connected thin-oxide device to achieve the very low protected node voltage (~2 V) required for advanced thin gate oxide technologies. In addition, for CMOS application, these all-NMOS (or PMOS) circuits would offer a high degree of latchup immunity. For both positive and negative spikes, single-pulse and repeated-pulse test data were obtained for six different test conditions. Electrical and physical analyses show dominant failure modes. Because techniques used to improve protection tend to degrade speed, a figure of merit is proposed to assist a fair comparison between different ESD protection circuit designs.