DocumentCode :
898861
Title :
Low cost architecture of direct conversion digital receiver
Author :
Gagné, J.F. ; Gauthier, J. ; Wu, K. ; Bosisio, R.G.
Author_Institution :
Dept. de Genie Electrique et Genie Informatique, Ecole Polytechnique de Montreal, Que., Canada
Volume :
151
Issue :
1
fYear :
2004
fDate :
2/1/2004 12:00:00 AM
Firstpage :
71
Lastpage :
76
Abstract :
The paper presents a low-cost architecture for a direct conversion digital receiver that uses six-port technology. An experimental prototype has been constructed and tested. Analogue carrier recovery and decision circuits are investigated as a means to provide future system integration and high data rate capacity. The designed receiver is operated at an ISM frequency of 2.45 GHz and uses a QPSK modulation format. Results on data rate limitations are given for QPSK signals up to 52 Mb/s. Test results related to adjacent channel, co-channel and CW interferences are presented for a data rate of 40 Mb/s. Phase offset between carrier and reference signals, along with carrier frequency deviation performances, are also presented for a rate of 40 Mb/s. A frequency hopping spread spectrum technique is discussed on the basis of the proposed architecture.
Keywords :
adjacent channel interference; cochannel interference; decision circuits; frequency hop communication; quadrature phase shift keying; radio receivers; spread spectrum communication; synchronisation; 2.45 GHz; 40 Mbit/s; CW interferences; ISM frequency; QPSK modulation; adjacent channel interferences; analogue carrier recovery; carrier frequency deviation; co-channel interferences; data rate capacity; decision circuits; direct conversion digital receiver; frequency hopping spread spectrum technique; six-port technology;
fLanguage :
English
Journal_Title :
Microwaves, Antennas and Propagation, IEE Proceedings
Publisher :
iet
ISSN :
1350-2417
Type :
jour
DOI :
10.1049/ip-map:20040049
Filename :
1267587
Link To Document :
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