• DocumentCode
    898875
  • Title

    Probability to achieve TSC goal

  • Author

    Lo, Jien-Chung ; Fujiwara, Eiji

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
  • Volume
    45
  • Issue
    4
  • fYear
    1996
  • fDate
    4/1/1996 12:00:00 AM
  • Firstpage
    450
  • Lastpage
    460
  • Abstract
    We propose a probabilistic measure for self-checking (SC) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-checking (TSC) goal at the lth cycle: TSCG(t). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the application environment and component failure rates. TSCG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. An SC circuit achieves TSC goal when no erroneous information or data is propagated beyond the boundary of this circuit. TSCG is therefore the probability that this fault confinement mechanism is intact. The SC properties are obtained through adding hardware redundancy to the original digital design, which means that an SC circuit has a higher failure rate than the original circuit. Further, there are tradeoffs between the level of hardware redundancy, the reliability, and the TSCG. We give several examples to clearly demonstrate these tradeoffs for different design environments. We emphasize that the TSCG is intended to provide a mean of dynamic error handling performance evaluation of SC designs. The TSC definitions and alike are still intact, since a cost-effective SC circuit must begin with a TSC circuit. The TSCG gives confidence in the use of cost-efficient error control codes and/or reduction in error handling capability. Analogous to reliability, the TSCG can be used in product specifications. This is a crucial step toward the practical applications of TSC or CED circuits
  • Keywords
    built-in self test; circuit reliability; error detection; fault tolerant computing; formal verification; logic CAD; logic testing; probability; TSCG; built in self test; circuit design; component failure rates; cost-efficient error control codes; dynamic error handling; error handling; failure rate; fault confinement; fault-tolerant systems; hardware redundancy; logic circuit testing; performance evaluation; probabilistic measure; reliability; self-checking circuits; totally self-checking; worst case dynamic behavior; Bridge circuits; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Error correction; Fault detection; Physical layer; Random variables;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.494102
  • Filename
    494102