A 35-ns 64K EEPROM

An extremely high-speed 8K/spl times/8 EEPROM has been fabricated in a 2-/spl mu/m double-poly CMOS floating gate technology. A typical address and chip enable access time of 35 ns has been achieved. Through a metal option, the device is compatible with 28-pin EEPROM, SRAM, or EPROM, or is a 24 pin bipolar PROM substitute. The high-speed access has been achieved with a fast single-ended sense amplifier, high-speed static bootstrapping techniques, a novel combination of static CMOS and depletion load technology, substrate bias, and high-performance layout. A new column and byte latch circuit implements a page-mode programming feature. Column redundancy implemented with EEPROM fuses increases manufacturability.