A triple-level wired 24K-gate CMOS gate array

A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design.