DocumentCode :
899199
Title :
Hybrid architecture for analogue neural network and its circuit implementation
Author :
Chen, L. ; Wedlake, M. ; Deliyannides, G. ; Kwok, H.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Volume :
143
Issue :
2
fYear :
1996
fDate :
4/1/1996 12:00:00 AM
Firstpage :
123
Lastpage :
128
Abstract :
The paper describes a prototype GaAs Hopfield neural network IC designed with a hybrid architecture. This architecture uses both parallel summation and multiplication, and the neuron states are updated serially. For an N×N network, only N multipliers (with an adder) and one activation (function) circuit are required. In the implementation, we have developed a 16 neuron network chip using CCDs to form the weight storage array. The main part of the chip (except for the CCDs) was fabricated using a 0.8 μm depletion mode self-aligned gate process and the chip was tested successfully when configured to operate as an associative memory
Keywords :
Hopfield neural nets; content-addressable storage; neural chips; 16 neuron network chip; CCDs; Hopfield neural network IC; analogue neural network; associative memory; circuit implementation; hybrid architecture;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:19960145
Filename :
494181
Link To Document :
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