A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS

Author

Cline, David W. ; Gray, Paul R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

31

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

294

Lastpage

303

Abstract

A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 μm CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit optimisation; integrated circuit design; pipeline processing; 1.2 micron; 13 bit; 166 mW; 5 MHz; 5 V; CMOS; differential nonlinearity; dynamic range; high swing residue amplifier; integral nonlinearity; per stage resolution; pipelined analog-to-digital converter; power dissipation minimisation; signal-to-noise plus distortion ratio; Analog-digital conversion; CMOS process; Circuits; Distortion; Dynamic range; High power amplifiers; Power dissipation; Prototypes; Signal processing; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.494191

Filename

494191