A CMOS gate array architecture for digital signal processing applications

A new CMOS gate array architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate array approach (macrocell design style), macrocells can be implemented efficiently on the new architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate array approach. In the common gate array approach, conventional gate array architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements