A scalable pipelined architecture for fast buffer SRAMs

Author

Nicol, C.J. ; Dickinson, A.G.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

Volume

31

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

419

Lastpage

429

Abstract

The design of synchronous buffer SRAMs for packet switching and signal processing applications is described. Called scalable cellular RAM (SCRAM), the approach configures memory blocks in a 2-D array with fully pipelined address and data distribution. The memory is scalable in that the access frequency is determined by the access time of a single block and is independent of the number of blocks. An experimental 0.5 μm CMOS 256 Kb SCRAM chip is described that operates at 240 MHz. Simulation results show that larger arrays are feasible using the suggested power reduction and redundancy techniques

Keywords

CMOS memory circuits; SRAM chips; buffer storage; memory architecture; pipeline processing; redundancy; 0.5 micron; 240 MHz; 256 Kbit; 2D array; CMOS chip; fast buffer SRAM; fully pipelined address distribution; packet switching applications; pipelined data distribution; power reduction techniques; redundancy techniques; scalable cellular RAM; scalable pipelined architecture; signal processing applications; static RAM; synchronous buffer SRAM; Bandwidth; BiCMOS integrated circuits; Decoding; Delay; Frequency; Packet switching; Random access memory; Read-write memory; Switches; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.494204

Filename

494204