A module generator for high-speed CMOS current output digital/analog converters

Author

Neff, Robert R. ; Gray, Paul R. ; Sangiovanni-Vincentelli, Alberto

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

31

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

448

Lastpage

451

Abstract

A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis, a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. Prototypes have been demonstrated for an 8-b, 100-MS/s specification, driving a 37.5-ohm video load, and a static 10-b specification, driving a 4 mA full-scale output current. Both designs use a 5-V supply in a 1.2 μm CMOS process

Keywords

CMOS integrated circuits; circuit optimisation; digital-analogue conversion; integrated circuit layout; mixed analogue-digital integrated circuits; 1.2 micron; 10 bit; 5 V; 8 bit; DSYN; circuit simulation; constrained optimization; design; high-speed CMOS current output digital/analog converters; layout; module generator; stretching; synthesis; tiling; video load; Analog-digital conversion; CMOS technology; Circuit simulation; Circuit synthesis; Constraint optimization; Coupling circuits; Design optimization; Equations; Optimization methods; Prototypes;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.494207

Filename

494207