Timing verification of dynamic circuits

Author

Venkat, Kumar ; Chen, Liang ; Lin, Ichiang ; Mistry, Piyush ; Madhani, Pravin

Author_Institution

Suryn Technol. Inc., San Jose, CA, USA

Volume

Issue

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

452

Lastpage

455

Abstract

A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits

Keywords

combinational circuits; computer testing; integrated circuit testing; logic testing; microprocessor chips; timing circuits; domino-style dynamic circuits; dynamic nodes; microprocessor circuits; static timing verifier; timing constraints; timing verification; Clocks; Coupling circuits; Energy consumption; Error correction; Latches; Logic; Microprocessors; Space vector pulse width modulation; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.494208

Filename

494208

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=899496