Delay-time evaluation in ED MOS logic LSI

An explicit formulation of the transient response of ED MOS logic gates is presented, including load conditions and driving waveforms. Defining delays as the time required by the current imbalance of the active inverter to charge or discharge the output load, with respect to physical reference levels, rise and fall mode delay times are obtained in an explicit formulation, with separate contributions due to fan-out and fan-in. Results are applied to ring oscillators and to depletion-load inverter chains with different configuration ratio values and are compared with SPICE simulations. With good agreement obtained, optimal structures with a low value of the configuration ratio can be defined. Analysis of propagation delay times in NOR, NAND, and transmission gates is given, allowing easy implementation of this model into logic simulators.