• DocumentCode
    900289
  • Title

    Estimating variation in IC yield estimates

  • Author

    Flack, Virginia Foard

  • Volume
    21
  • Issue
    2
  • fYear
    1986
  • fDate
    4/1/1986 12:00:00 AM
  • Firstpage
    362
  • Lastpage
    365
  • Abstract
    Many methods have been proposed for obtaining IC yield estimates as IC areas increase. These estimates are by their very nature variable. The variability of the proposed yield estimates has not yet been discussed in the literature. The author describes a method for deriving formulas for the variance and standard deviation of yield estimates, using Stapper´s negative binomial model as a detailed example. Computations based on Moore´s half-slice data give standard deviations near 3.0% for different die areas.
  • Keywords
    Integrated circuit manufacture; Integrated circuit technology; integrated circuit manufacture; integrated circuit technology; Equations; Helium; Integrated circuit modeling; Maximum likelihood estimation; Parameter estimation; Predictive models; Random variables; Read only memory; Semiconductor device modeling; Yield estimation;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1986.1052528
  • Filename
    1052528