A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme

In this paper, a new GF(2^m) multiplier for standard-basis representation is developed. The proposed multiplier implements the Mastrovito multiplication scheme and can be designed for every field GF(2^m). A minimum-area implementation of the first block of Mastrovito multiplier and a high-speed delay-driven tree architecture for the second block of the Mastrovito multiplier are employed in the new circuit. Multiplier complexity and delay are analytically evaluated for many polynomial classes. Timing and area occupation performances of the proposed multiplier are also calculated for many fields used in Reed-Solomon codes applications and compared with those of previously proposed solutions. The comparison shows that the proposed multiplier outperforms previous architectures for every considered GF(2^m) field. The effectiveness of the proposed solution in a real application is verified by implementing in a 0.25 mum CMOS technology the key equation solving block of a (255, 239) Reed-Solomon decoder. The use of the proposed multiplier in this application results in a substantial speed improvement without any penalty in the silicon area occupation.