Abstract :
Logic designers are making increasing use of hardware-description languages (HDLs), special-purpose languages designed to support the design of digital hardware. Examples include Ella, Helix, Verilog and VHDL. In general, use of an HDL allows a designer to evaluate a number of different hardware architectures before becoming committed to the details of a design. To achieve fast, efficient gate-level implementations of the random, unstructured parts of chips (e.g. controllers), designers are turning increasingly to a range of CAD tools known collectively as logic synthesis. Such tools can minimise the area occupied by random logic as well as an experienced designer can, and can significantly reduce the overall time to market for a design. The author discusses both of these techniques and how they can be combined by using HDLs as the input to logic synthesis. One such example, Locam, is described
