Compensation of bipolar monolithic circuits using the parasitic capacitance of diffused resistors

A method of compensating bipolar integrated circuits which uses the parasitic capacitance of diffused resistors is studied. The advantages over other methods are: compatibility with the standard bipolar fabrication process, ease of implementation, and the possibility of controlling the overall bandwidth of an amplifier through adjustment of the bias of a resistor (for variable bandwidth applications or for compensation of process variations). The main drawback is the large size required. The sensitivity to process-parameter variations of the resulting compensation is shown to be comparable to that achieved with a MOS or N/SUP +/P capacitor. The MOS compensation is more stable with temperature variations. The diffused resistor models are shown to yield accurate results as long as a sufficient number of lumped sections are used when large area resistors are considered.