• DocumentCode
    900809
  • Title

    A full adder using junction charge-coupled logic

  • Author

    Van Der Klauw, Cornelis L M

  • Volume
    21
  • Issue
    4
  • fYear
    1986
  • fDate
    8/1/1986 12:00:00 AM
  • Firstpage
    584
  • Lastpage
    587
  • Abstract
    A full adder that is based on three-dimensional charge transport in junction charge-coupled devices (JCCDs) is presented. The basic current uses little chip area and is operated by a three-phase clock. No DC voltages are required for logic operation. The SUM and CARRY signals are calculated within one clock cycle. The concept of this full adder is suited to application in systolic arrays.
  • Keywords
    Adders; Charge-coupled device circuits; adders; charge-coupled device circuits; Adders; Charge coupled devices; Circuits; Clocks; Communication switching; Computational modeling; Electrons; Logic; Signal processing algorithms; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1986.1052576
  • Filename
    1052576
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=900809