Title :
13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology
Author :
Ogiue, Katsumi ; Odaka, Masanori ; Miyaoka, Shuuichi ; Masuda, Ikuro ; Ikeda, Takahide ; Tonomura, Kenichi
fDate :
10/1/1986 12:00:00 AM
Abstract :
The development is discussed for a 13-ns, 500-mW, 16K word×4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS) technology that combines a bipolar and a CMOS device on the same chip. The power dissipation of the RAM is about one half that of the conventional 64-kb bipolar ECL RAM. This high-speed, low-power RAM has been realized through a concept of a MOS-type memory cell, bipolar circuits, and a CMOS combination gate to allow for increased LSI integration.
Keywords :
Emitter-coupled logic; Integrated memory circuits; Monolithic integrated circuits; Random-access storage; emitter-coupled logic; integrated memory circuits; monolithic integrated circuits; random-access storage; Analytical models; CMOS technology; Circuit simulation; Driver circuits; Large scale integration; Paper technology; Power dissipation; Production; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052595
