DocumentCode
901042
Title
A 15-ns CMOS 64K RAM
Author
Schuster, Stanley E. ; Chappell, Barbara A. ; Franch, Robert L. ; Greier, Paul F. ; Klepner, Stephen P. ; Lai, Fang-Shi J. ; Cook, Peter W. ; Lipa, Robert A. ; Perry, Reginald J. ; Pokorny, William F. ; Roberge, Michael A.
Volume
21
Issue
5
fYear
1986
fDate
10/1/1986 12:00:00 AM
Firstpage
704
Lastpage
712
Abstract
The RAM was built using a technology with self-aligned TiSi/SUB 2/, single-level metal, an average minimum feature size of 1.35 μm, and a minimum effective channel length of 1.1 μm. An access of 10 ns is possible with the word line stitched on a second level of metal and some minor redesign. High speed is achieved through innovative circuits and design concepts. Novel CMOS circuits include a sense-amp set signal generator, a row decoder, and an input circuit. A layout-rule-independent graphics tool, which was used for the artwork design, is discussed.
Keywords
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; CMOS technology; Circuits; Decoding; FETs; Graphics; Helium; MOS devices; Random access memory; Read-write memory; Signal generators;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052598
Filename
1052598
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