An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell

A novel single-polysilicon EEPROM cell, called DIFLOX (diffused layer controlled floating-gate-type cell with thin oxide), has been used in this experimental memory. The floating-gate voltage is controlled by two thin-oxide capacitors coupled with two N/SUP +/ diffused layers: the drain and the control gate. Its size is reduced to 86.25 μm/SUP 2/ by 1.2-μm photolithography and scaled transistors with 1.4-μm gate length. For programming time reduction, a page-mode programming scheme was used. Successive data of up to 16 bytes can be loaded into internal storage and programmed simultaneously. All high voltages needed to perform the ERASE/PROGRAM function are generated internally, and two kinds of timers were designed using an improved switched-capacitor technique. Owing to the open-bit-line scheme, cell data were detected with high sensitivity in spite of the large-bit-line and word-line parasitic capacitance. The EEPROM typically achieves a 150-ns address access time, with an 80-mW active and 1-μW standby power dissipation. It was successfully fabricated in a single-polysilicon and single-metal CMOS process. The chip is 7.33×6.23 mm/SUP 2/ and is packed into the DIP 28 pin, which is pin-to-pin compatible to a 256-kb SRAM.