• DocumentCode
    901253
  • Title

    A subnanosecond HEMT 1-kbit static RAM

  • Author

    Nishiuchi, Koichi ; Kobayashi, Naoki ; Kuroda, Shigeru ; Notomi, Seishi ; Mimura, Takashi ; Abe, Masayiuki ; Kobayashi, Masaaki

  • Volume
    21
  • Issue
    5
  • fYear
    1986
  • fDate
    10/1/1986 12:00:00 AM
  • Firstpage
    869
  • Lastpage
    874
  • Abstract
    The RAM has a memory capacity of 1024 bits and integrates 7244 high-electron-mobility transistor (HEMT) devices into 1024-words×1-bit organization. The RAM uses enhancement/depletion-type direct-coupled FET logic (DCFL) circuitry as a basic circuit and can operate fully statically. The design rules used are a 1.5-μm minimum gate length, a 2×2-μm/SUP 2/ contact hole, and a 3-μm linewidth and spacing of the wiring electrodes. The memory cell is 55×39 μm and the chip is 3.0×2.9 mm. The RAM is fabricated on an AlGaAs/GaAs heterojunction epi-structure grown by molecular beam epitaxy on a Cr-doped 2-in LEC GaAs substrate wafer. A subnanosecond access time of 0.87 ns with a 1.60-V supply and 360-mW dissipation has been attained at liquid nitrogen temperature.
  • Keywords
    Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Electrodes; FETs; Gallium arsenide; HEMTs; Logic circuits; Logic devices; MODFETs; Random access memory; Read-write memory; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1986.1052619
  • Filename
    1052619