Elimination of process-dependent clock skew in CMOS VLSI

Delays of two clock signals propagating along their respective CMOS logic circuit paths can be matched against all processing variations if the sum of the pull-up delays of PFETs along the first signal path is matched to that of the second path, and if the sum of the pull-down delays of NFETs along the first path is matched to that of the second path. This design technique allows generation of a skewless pair of upgoing and downgoing CMOS clocks, and the technique allows the design of CMOS VLSI free from process-induced race conditions. The technique is flexible for light or heavy clock load and for the choice of decoder logic. The technique has a wide application in MOS circuits other than clock decoders.