A high-performance 1-Mbit dynamic RAM with a folded capacitor cell

The DRAM was fabricated using buried oxide (BOX) isolation technology and a two-level aluminium metallization scheme. High-speed operation has been realized by a newly developed high-speed sensing system along with reduced word-line resistances, using double-level aluminium metallization. Low-power operation has been achieved by incorporating a partial activation scheme of memory cell arrays and reducing the bit-line capacitance. The typical CAS access time of the chip is 30 ns and the active power dissipation is typically 270 mW at 260-ns cycle time.