DocumentCode :
902193
Title :
Architectures and design techniques for real-time image-processing IC´s
Author :
Ruetz, Peter A. ; Brodersen, Robert W.
Volume :
22
Issue :
2
fYear :
1987
fDate :
4/1/1987 12:00:00 AM
Firstpage :
233
Lastpage :
250
Abstract :
A set of eight chips that perform real-time image-processing tasks was designed and fabricated with a 4-μm NMOS technology. The chips include a 3×3 linear convolver, a 3×3 sorting filter, a 7×7 logical convolver, a contour tracer, a feature extractor, a lookup-table ROM, and two postprocessors for the linear convolver. All chips were designed with architectures that are dedicated to the particular image-processing task to be performed. The image-processing circuits operate on 10-MHz video data (512×512-pixel images). The design time for the chips was kept to 1.5 man-years by reusing hardware and using (and developing) appropriate CAD tools, ROM generators and a data-path generator were developed to reduce the circuit design time. An image recognition system was built with these custom chips that can recognize two-dimensional objects that are characterized by their closed outer contours. The complete system is controlled by a Sun workstation and operates at rates up to 15 frames/s. The recognition system achieved a 98% recognition rate for eight objects over a wide range of orientation and size variations and a 100% recognition rate without size variations.
Keywords :
Computerised picture processing; Field effect integrated circuits; Microprocessor chips; Real-time systems; computerised picture processing; field effect integrated circuits; microprocessor chips; real-time systems; Circuits; Convolvers; Data mining; Feature extraction; Hardware; Image recognition; MOS devices; Nonlinear filters; Read only memory; Sorting;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1987.1052708
Filename :
1052708
Link To Document :
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