Large-signal linearity of scaled MOS transistors

The tendency toward linearity between saturated drain current and gate-to-source voltage exhibited by small-dimension MOS transistors is explored from the standpoint of possible exploitation in analog MOS circuits. Nonlinearity is calculated using a simple MOS model which includes the high field dependence of inversion-layer carrier mobility. The nonlinearity for devices with a wide range of channel lengths and gate dielectric thicknesses was measured and is compared to results from the model. Some problems associated with the use of short-channel MOS transistors in analog circuits are discussed.