A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology

Author

Masuoka, Fujio ; Asano, Masamichi ; Iwahashi, Hiroshi ; Komuro, Teisuke ; Tozawa, Noriyoshi ; Tanaka, Shinichi

Volume

22

Issue

4

fYear

1987

fDate

8/1/1987 12:00:00 AM

Firstpage

548

Lastpage

552

Abstract

A high-density 256-kb flash electrically erasable PROM (E/SUP 2/PROM) with a single transistor per bit has been developed by utilizing triple-polysilicon technology. As a result of achieving a novel compact cell that is as small as 8×8 μm/SUP 2/, even with relatively conservative 2.0-μm design rules, a small die size of 5.69×5.78 mm/SUP 2/ is realized. This flash E/SUP 2/PROM is fully pin-compatible with a 256-kb UV-EPROM without increasing the number of input pins for erasing by introducing a novel programming and erasing scheme. Programming time is as fast as 200 μs/byte and erasing time is less than 100 ms per chip. A typical access time of 90 ns is achieved by using sense-amplifier circuitry.

Keywords

Field effect integrated circuits; Integrated memory circuits; PROM; field effect integrated circuits; integrated memory circuits; Ceramics; Circuit synthesis; EPROM; Mass production; Microelectronics; PROM; Pins; Plastic integrated circuit packaging; Plastic packaging; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1987.1052771

Filename

1052771