Title :
Partially depleted SOI MOSFETs under uniaxial tensile strain
Author :
Zhao, Wei ; He, Jianli ; Belford, Rona E. ; Wernersson, Lars-Erik ; Seabaugh, Alan
Author_Institution :
Dept. of Electr. Eng., Univ. of Notre Dame, IN, USA
fDate :
3/1/2004 12:00:00 AM
Abstract :
The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 μm. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 μm, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.
Keywords :
MOSFET; silicon-on-insulator; tensile strength; DC performance; bulk silicon MOSFETs; current flow direction; drain current tracks; gate length; gate orientation; gate voltage characteristics; longitudinal strain orientations; low-field electron mobility; low-field hole mobility; mechanical stress; mobility enhancement; n-channel MOSFET; p-channel MOSFET; partially depleted SOI MOSFETs; partially depleted silicon-on-insulator; piezoresistance coefficients; silicon inversion layer; threshold voltage; transverse strain orientations; uniaxial tensile strain; Capacitive sensors; Charge carrier processes; Electron mobility; Helium; MOSFET circuits; Piezoresistance; Silicon on insulator technology; Stress; Tensile strain; Uniaxial strain;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2003.823048