A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9×16.11 mm/SUP 2/ has been fabricated using a 0.9-μm twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5×5.5 μm/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-μA standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.