Circuit design guidelines for n-channel MOSFET hot carrier robustness

Author

Mistry, Kaizad R. ; Fox, Thomas F. ; Preston, Ronald P. ; Arora, Narain D. ; Doyle, Brian S. ; Nelsen, Donald E.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

Volume

40

Issue

7

fYear

1993

fDate

7/1/1993 12:00:00 AM

Firstpage

1284

Lastpage

1295

Abstract

Reviews present understanding of the AC stress effect in n-MOSFETs, defining and parameterizing the AC stress model. The authors incorporate the AC hot-carrier model into a circuit-level hot-carrier reliability simulator, ADHOC, that works in concert with SPICE. Sources of on-chip voltage excursions above the nominal value of the power supply V_dd are explored, and this information is used to develop a set of design guidelines at the transistor level. The hot-carrier reliability of a broad class of basic circuit building blocks is then simulated and used as the basis for a comprehensive set of design guidelines at the transistor and circuit levels

Keywords

MOS integrated circuits; SPICE; circuit reliability; digital simulation; hot carriers; insulated gate field effect transistors; semiconductor device models; AC stress effect; AC stress model; ADHOC; SPICE; circuit-level hot-carrier reliability simulator; design guidelines; hot carrier robustness; n-channel MOSFET; on-chip voltage excursions; power supply; Capacitance; Circuit simulation; Circuit synthesis; Degradation; Guidelines; Hot carriers; MOSFET circuits; Robustness; Stress; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.216434

Filename

216434