A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K×8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-μA standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-μm twin-tub CMOS technology has been developed to realize the 5.6×9.5-μ/SUP 2/ cell size and the 6.86×15.37-mm/SUP 2/ chip size.