Title :
CRISP: a pipelined 32-bit microprocessor with 13-kbit of cache memory
Author :
Berenbaum, Alan D. ; Colbry, Brian W. ; Ditzel, David R. ; Freeman, Don R. ; McLellan, Hubert R. ; O´Connor, Kevin J. ; Shoji, Masakazu
fDate :
10/1/1987 12:00:00 AM
Abstract :
The implementation and architecture of a 172, 163-transistor single-chip general-purpose 32-b microprocessor is described. The 16-MHz chip is fabricated using a single-metal double-poly 1.75-μm CMOS technology and is capable of a peak execution rate of over one instruction/clock. Multiple on-chip catches, pipelining, and a one-cycle I/O protocol are utilized.
Keywords :
Buffer storage; CMOS integrated circuits; Microprocessor chips; Pipeline processing; buffer storage; microprocessor chips; pipeline processing; CMOS technology; Cache memory; Central Processing Unit; Clocks; Computer architecture; Encoding; Hardware; Microprocessors; Reduced instruction set computing; Senior members;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052813
