Title :
Selector-line merged built-in ECC technique for DRAMs
fDate :
10/1/1987 12:00:00 AM
Abstract :
A high-performance built-in error checking and correcting (ECC) technique applicable to megabit-level dynamic RAM (DRAM) chips is described. This technique, based on a bidirectional parity code, achieves high-speed error correction with a minimum increase in area. The impact of the technique on access time and chip overhead is discussed. Furthermore, effects on soft-error reduction and yield improvement are analytically investigated.
Keywords :
Error correction; Error detection; Integrated memory circuits; Random-access storage; error correction; error detection; integrated memory circuits; random-access storage; DRAM chips; Error analysis; Error correction; Error correction codes; Fabrication; Helium; Integrated circuit technology; Integrated circuit yield; Redundancy; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052826
