Analysis and modelling of initial delay time and its impact on propagation delay of CMOS logic gates

The initial delay times due to the capacitive feedthrough effects in CMOS inverters are characterised and investigated. Based on the MOSFET large-signal model, the initial delay is modelled for a chain of CMOS inverters under step and ramp inputs. Optimal design that results in the minimum initial delay is obtained. Correlation between the initial delay and the propagation delay is constructed in the case of characteristic waveforms. The initial delays are found to determine the propagation delay. Applying the model to evaluate the speed performance of a scaled-down CMOS, the delay improvements for various scaling laws are compared. It is found that the most effective law in reducing the initial delay for internal circuits is the constant voltage law, whereas that for the input stage is the constant electric field law. Comparisons to SPICE simulation results are also given and good agreement is achieved.