Performance features of the PA7100 microprocessor

Author

Asprey, Tom ; Averill, Gregory S. ; Delano, Eric ; Mason, Russ ; Weiner, Bill ; Yetter, Jeff

Author_Institution

Hewlett-Packard, Fort Collins, CO, USA

Volume

13

Issue

3

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

22

Lastpage

35

Abstract

The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar execution and supports clock rates of up to 100 MHz in standard 0.8- mu m CMOS. Features such as a flexible primary cache organization and multiprocessing capability allow the device to be scaled to a variety of system applications, price ranges, and performance levels. The microprocessor instruction execution pipeline, cache design, translation look-aside buffer (TLB) for virtual address translation, floating-point unit, and system interface bus are discussed. The design, test, and verification methods used in the development of the PA7100 are reviewed.<>

Keywords

microprocessor chips; reduced instruction set computing; PA-RISC; PA7100 CPU; cache design; floating-point unit; microprocessor instruction execution pipeline; precision-architecture; reduced-instruction-set-computer; system interface bus; translation look-aside buffer; verification; virtual address translation; CMOS technology; Central Processing Unit; Circuits; Clocks; Coprocessors; Frequency; Memory management; Microprocessors; Pipelines; Random access memory;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.216746

Filename

216746