A General Purpose FASTBUS Interface Chipset

A design concept is presented for a set of semicustom integrated circuits which will interface a master or slave module to a FASTBUS segment. These devices will perform master arbitration, address recognition, handshaking, data pipe-lining and many other standard FASTBUS protocol tasks. Gate arrays are used to implement designs which would require one hundred or more normal integrated circuits, thus greatly reducing the area of a FASTBUS printed circuit board needed for the interface.