CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s